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18-mb (512k x 36/1m x 18) flow-through sram cy7c1381c cy7c1383c cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05238 rev. *b revised february 26, 2004 features ? supports 133-mhz bus operations ? 512k x 36/1m x 18 common i/o ? 3.3v ?5% and +10% core power supply (v dd ) ? 2.5v or 3.3v i/o supply (v ddq ) ? fast clock-to-output times ? 6.5 ns (133-mhz version) ? 7.5 ns (117-mhz version) ? 8.5 ns (100-mhz version) ? provide high-performance 2-1-1-1 access rate ? user-selectable burst counter supporting intel ? pentium ? interleaved or linear burst sequences ? separate processor and controller address strobes ? synchronous self-timed write ? asynchronous output enable ? offered in jedec-standard 100-pin tqfp ,119-ball bga and 165-ball fbga packages ? jtag boundary scan for bga and fbga packages ? ?zz? sleep mode option functional description [1] the cy7c1381c/cy7c1383c is a 3.3v, 512k x 36 and 1m x 18 synchronous flowthrough srams, respectively designed to interface with high-speed microprocessors with minimum glue logic. maximum access dela y from clock rise is 6.5 ns (133-mhz version). a 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable ( ce 1 ), depth-expansion chip enables (ce 2 and ce 3 [2] ), burst control inputs ( adsc , adsp , and adv ), write enables ( bw x , and bwe ), and global write ( gw ). asynchronous inputs include the output enable ( oe ) and the zz pin . the cy7c1381c/cy7c1383c allows either interleaved or linear burst sequences, selected by the mode input pin. a high selects an interleaved burst sequence, while a low selects a linear burst sequence. burst accesses can be initiated with the proces sor address strobe (adsp ) or the cache controller address strobe (adsc ) inputs. address advancement is controlled by the address advancement (adv ) input. addresses and chip enables are registered at rising edge of clock when either address strobe processor ( adsp ) or address strobe controller ( adsc ) are active. subsequent burst addresses can be internally generated as controlled by the advance pin ( adv ). the cy7c1381c/cy7c1383c operates from a +3.3v core power supply while all outputs may operate with either a +2.5 or +3.3v supply. all inputs and outputs are jedec-standard jesd8-5-compatible. selection guide 133 mhz 117 mhz 100 mhz unit maximum access time 6.5 7.5 8.5 ns maximum operating current 210 190 175 ma maximum cmos standby current 70 70 70 ma 1 2 3 4 5 6 notes: 1. for best?practices recommendations, please refer to the cypress application note system design guidelines on www.cypress.com. 2. ce 3, ce 2 are for tqfp and 165 fbga package only. 119 bga is offered only in 1 chip enable.
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 2 of 36 c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b memory array e input register address register write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 adv/ld ce adv/ld c c lk c en write drivers d a t a s t e e r i n g s e n s e a m p s write address register a0, a1, a o u t p u t b u f f e r s e zz sleep control 7 8 address register burst counter and logic clr q1 q0 enable register sense amps output buffers input registers memory array mode a [1:0] zz dq s dqp a dqp b dqp c dqp d a 0, a1, a adv clk adsp adsc bw d bw c bw b bw a bwe ce1 ce2 ce3 oe gw sleep control dq a , dqp a byte write register dq b , dqp b byte write register dq c , dqp c byte write register byte write register dq d , dqp d byte write register dq d , dqp d byte write register dq c , dqp c byte write register dq b , dqp b byte write register dq a , dqp a byte write register logic block diagram ? cy7c1381c (512k x 36) address register adv clk burst counter and logic clr q1 q0 adsc ce 1 oe sense amps memory array adsp output buffers input registers mode ce 2 ce 3 gw bwe a 0,a1,a bw b bw a dq b ,dqp b write register dq a ,dqp a write register enable register a[1:0] dqs dqp a dqp b dq b ,dqp b write driver dq a ,dqp a write driver sleep control zz logic block diagram ? cy7c1383c (1m x 18)
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 3 of 36 pin configurations a a a a a 1 a 0 nc nc v ss v dd a a a a a a a a dqp b dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1381c (512k x 36) v ss /dnu a a a a a 1 a 0 nc nc v ss v dd a a a a a a a a a nc nc v ddq v ssq nc dqp a dq a dq a v ssq v ddq dq a dq a v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a nc nc v ssq v ddq nc nc nc nc nc nc v ddq v ssq nc nc dq b dq b v ssq v ddq dq b dq b v dd nc v ss dq b dq b v ddq v ssq dq b dq b dqp b nc v ssq v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1383c (1m x 18) v ss /dnu 100-pin tqfp pinout a a
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 4 of 36 pin configurations (continued) 234567 1 a b c d e f g h j k l m n p r t u v ddq nc nc dqp c dq c dq d dq c dq d aa aa adsp v ddq aa dq c v ddq dq c v ddq v ddq v ddq dq d dq d nc nc v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc nc nc nc tdo tck tdi tms nc nc nc v ddq v ddq v ddq aaa a a a a a a a a a0 a1 dq a dq c dq a dq a dq a dq b dq b dq b dq b dq b dq b dq b dq a dq a dq a dq a dq b v dd dq c dq c dq c v dd dq d dq d dq d dq d adsc nc ce 1 oe adv gw v ss v ss v ss v ss v ss v ss v ss v ss dqp a mode dqp d dqp b bw b bw c nc v dd nc bw a nc bwe bw d zz 2 34567 1 a b c d e f g h j k l m n p r t u v ddq nc nc nc dq b dq b dq b dq b aa aa adsp v ddq aa nc v ddq nc v ddq v ddq v ddq nc nc nc nc v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc nc nc nc tdo tck tdi tms a a nc v ddq v ddq v ddq anca a a a a a a a a a0 a1 dq a dq b nc nc dq a nc dq a dq a nc nc dq a nc dq a nc dq a nc dq a v dd nc dq b nc v dd dq b nc dq b nc adsc nc ce 1 oe adv gw v ss v ss v ss v ss v ss v ss v ss v ss nc mode dqp b dqp a v ss bw b nc v dd nc bw a nc bwe v ss zz cy7c1383c (1m x 18) cy7c1381c (512k x 36) 119-ball bga (1 chip enable with jtag)
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 5 of 36 pin configurations (continued) 165-ball fbga (3 chip enable) cy7c1381c (512k x 36) 234 567 1 a b c d e f g h j k l m n p r tdo nc / 288m nc dqp c dq c dqp d nc dq d ce 1 bw b ce 3 bw c bwe a ce 2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d nc / 36m nc / 72m v ddq bw d bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq c v ss dq c v ss dq c dq c v ss v ss v ss v ss v ss nc v ss a1 dq d dq d nc nc v ddq v ss tms 891011 a adv a adsc nc oe adsp a nc / 144m v ss v ddq nc dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a cy7c1383c (1m x 18) a0 a v ss 234 567 1 a b c d e f g h j k l m n p r tdo nc / 288m nc nc nc dqp b v ss dq b ace 1 nc ce 3 bw b bwe a ce 2 nc dq b dq b mode nc dq b dq b nc nc nc nc / 36m nc / 72m v ddq nc bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq b v ss nc v ss dq b nc v ss v ss v ss v ss v ss nc v ss a1 dq b nc nc nc v ddq v ss tms 891011 a adv a adsc a oe adsp a nc / 144m v ss v ddq nc dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a a a
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 6 of 36 cy7c1381c?pin definitions name tqfp (3-chip enable) bga (1-chip enable) fbga (3-chip enable) i/o description a 0 , a 1 , a 37,36,32,33,34, 35,42,43,44,45, 46,47,48,49,50, 81,82,99,100 p4,n4,a2,b2,c2 ,r2,a3,b3,c3,t 3,t4,a5,b5,c5, t5,a6,b6,c6,r6 r6,p6,a2,a10, b2,b10,n6,p3, p4,p8,p9,p10, p11,r3,r4,r8, r9,r10,r11 input- synchronous address inputs used to select one of the 512k address location s. sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 [2] are sampled active. a [1:0] feed the 2-bit counter. bw a, bw b bw c, bw d 93,94,95,96 l5,g5,g3,l3 b5,a5,a4,b4 input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw 88 h4 b7 input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes are written, regardless of the values on bw [a:d] and bwe ). clk 89 k4 b6 input- clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 98 e4 a3 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 [2] to select/deselect the device. adsp is ignored if ce 1 is high. ce 2 97 - b3 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 [2] to select/deselect the device. ce 3 [2] 92 - a6 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. oe 86 f4 b8 input- asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv 83 g4 a9 input- synchronous advance input signal, sampled on the rising edge of clk . when asserted, it automatically increments the address in a burst cycle. adsp 84 a4 b9 input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 7 of 36 adsc 85 b4 a8 input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized . bwe 87 m4 a7 input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. zz 64 t7 h11 input- asynchronous zz ?sleep? input, active high . when asserted high places the device in a non-time-critical ?sleep? condition with data integrity preserved. for normal operation, this pin has to be low or left floating. zz pin has an internal pull-down. dq s 52,53,56,57,58, 59,62,63,68,69, 72,73,74,75,78, 79,2,3,6,7,8,9, 12,13,18,19,22, 23,24,25,28,29 k6,l6,m6,n6,k7 ,l7,n7,p7,e6,f 6,g6,h6,d7,e7, g7,h7,d1,e1,g 1,h1,e2,f2,g2, h2,k1,l1,n1,p1 ,k2,l2,m2,n2 m11,l11,k11, j11,j10,k10, l10,m10,d10, e10,f10,g10, d11,e11,f11, g11,d1,e1, f1,g1,d2,e2, f2,g2,j1,k1, l1,m1,j2, k2,l2,m2, i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dq s and dqp [a:d] are placed in a tri-state condition. the outputs are automatically tri-stat ed during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of oe . dqp [a:d] 51,80,1,30 p6,d6,d2,p2 n11,c11,c1,n1 i/o- synchronous bidirectional data parity i/o lines. functionally, these signals are identical to dq s . during write sequences, dqp [a:d] is controlled by bw [a:d] correspondingly. mode 31 r3 r1 input-static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. this is a strap pin and should remain static during device operation. mode pin has an internal pull-up. v dd 15,41,65,91 j2,c4,j4 ,r4,j6 d4,d8,e4, e8,f4,f8, g4,g8,h4, h8,j4,j8, k4,k8,l4, l8,m4,m8 power supply power supply inputs to the core of the device . cy7c1381c?pin definitions (continued) name tqfp (3-chip enable) bga (1-chip enable) fbga (3-chip enable) i/o description
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 8 of 36 v ddq 4,11,20,27, 54,61,70,77 a1,f1,j1,m1,u1 , a7,f7,j7,m7,u7 c3,c9,d3, d9,e3,e9, f3,f9,g3, g9,j3,j9, k3,k9,l3, l9,m3,m9, n3,n9 i/o power supply power supply for the i/o circuitry . v ss 17,40,67,90 h2,d3,e3,f3,h3 ,k3, m3,n3, p3,d5,e5,f5,h5 ,k5, m5,n5,p5 c4,c5,c6, c7,c8,d5, d6,d7,e5, e6,e7,f5, f6,f7,g5, g6,g7,h5, h6,h7,j5, j6,j7,k5,k6,k7, l5,l6,l7,m5,m6 ,m7,n4,n8 ground ground for the core of the device . v ssq 5,10,21,26, 55,60,71,76 - - i/o ground ground for the i/o circuitry . tdo - u5 p7 jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. if the jtag feature is not being utilized, this pin should be left unconnected. this pin is not available on tqfp packages. tdi - u3 p5 jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being utilized, this pin can be left floating or connected to v dd through a pull up resistor. this pin is not available on tqfp packages. tms - u2 r5 jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being utilized, this pin can be discon- nected or connected to v dd . this pin is not available on tqfp packages. tck - u4 r7 jtag-clock clock input to the jtag circuitry . if the jtag feature is not being utilized, this pin must be connected to v ss . this pin is not available on tqfp packages. nc 16,38,39,66 b1,c1,r1,t1,t2 ,j3,d4,l4,j5,r5 ,t6,u6,b7,c7,r 7 a1,a11,b1, b11,c2,c10,h1, h3,h9, h10,n2,n5,n7, n10,p1,p2,r2 - no connects . not internally connected to the die. 18m, 36m, 72m, 144m and 288m are address expansion pins are not internally connected to the die. v ss /dnu 14 - - ground/dnu this pin can be connected to ground or should be left floating. cy7c1381c?pin definitions (continued) name tqfp (3-chip enable) bga (1-chip enable) fbga (3-chip enable) i/o description
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 9 of 36 cy7c1383c:pin definitions name tqfp (3-chip enable) bga (1-chip enable) fbga (3-chip enable) i/o description a 0 , a 1 , a 37,36,32,33,34, 35,42,43,44,45, 46,47,48,49,50, 80,81,82,99,100 p4,n4,a2,b2, c2,r2,t2,a3, b3,c3,t3,a5, b5,c5,t5,a6, b6,c6,r6,t6 r6,p6,a2, a10,a11,b2, b10,n6,p3,p4, p8,p9,p10, p11,r3,r4, r8,r9,r10,r11 input- synchronous address inputs used to select one of the 1m address locations . sampled at the ris- ing edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 [2] are sampled active. a [1:0] feed the 2-bit counter. bw a, bw b 93,94 l5,g3 b5,a4 input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw 88 h4 b7 input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes are written, regardless of the values on bw [a:b] and bwe ). bwe 87 m4 a7 input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk 89 k4 b6 input- clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 98 e4 a3 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 [2] to select/deselect the device. adsp is ignored if ce 1 is high. ce 2 97 - b3 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 [2] to select/deselect the device. ce 3 [2] 92 - a6 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. oe 86 f4 b8 input- asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deassert ed high, i/o pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv 83 g4 a9 input- synchronous advance input signal, sampled on the rising edge of clk . when asserted, it automatically increments the address in a burst cycle.
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 10 of 36 adsp 84 a4 b9 input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high adsc 85 b4 a8 input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized . zz 64 t7 h11 input- asynchronous zz ?sleep? input, active high . when asserted high places the device in a non-time-critical ?sleep? condition with data integrity preserved. for normal operation, this pin has to be low or left floating. zz pin has an internal pull-down. dq s 58,59,62,63,68, 69,72,73,8,9,12, 13, 18,19,22,23 p7,k7,g7,e7,f6 ,h6,l6,n6,d1,h 1,l1,n1,e2,g2, k2,m2 j10,k10, l10,m10, d11,e11, f11,g11,j1,k1, l1,m1, d2,e2,f2, g2 i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dq s and dqp [a:b] are placed in a tri-state condition. the outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the dev ice is deselected, regardless of the state of oe . dqp [a:b] 74,24 d6,p2 c11,n1 i/o- synchronous bidirectional data parity i/o lines. functionally, these signals are identical to dq s . during write sequences, dqp [a:b] is controlled by bw [a:b] correspondingly. mode 31 r3 r1 input-static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. this is a strap pin and should remain static during device operation. mode pin has an internal pull-up. cy7c1383c:pin definitions (continued) name tqfp (3-chip enable) bga (1-chip enable) fbga (3-chip enable) i/o description
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 11 of 36 v dd 15,41,65,91 c4,j2,j4,j6,r4 d4,d8,e4, e8,f4,f8, g4,g8, h4,h8,j4, j8,k4,k8, l4,l8,m4, m8 power supply power supply inputs to the core of the device . v ddq 4,11,20,27, 54,61,70,77 a1,a7,f1,f7,j1, j7,m1,m7,u1,u 7 c3,c9,d3, d9,e3,e9, f3,f9,g3, g9,j3,j9, k3,k9,l3, l9,m3,m9, n3,n9 i/o power supply power supply for the i/o circuitry . v ss 17,40,67,90 d3,d5,e3,e5,f3 ,f5,g5,h3, h5,k3,k5,l3,m3 , m5,n3, n5,p3,p5 c4,c5,c6, c7,c8,d5, d6,d7,e5, e6,e7,f5, f6,f7,g5, g6,g7,h1, h2,h5,h6, h7,j5,j6,j7,k5, k6,k7,l5,l6,l7, m5, m6,m7,n4, n8 ground ground for the core of the device . v ssq 5,10,21,26, 55,60,71,76, - - i/o ground ground for the i/o circuitry . tdo - u5 p7 jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. if the jtag feature is not being utilized, this pin should be left unconnected. this pin is not available on tqfp packages. tdi - u3 p5 jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being utilized, this pin can be left floating or connected to v dd through a pull up resistor. this pin is not available on tqfp packages. tms - u2 r5 jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being utilized, this pin can be disconnected or connected to v dd . this pin is not available on tqfp packages. tck - u4 r7 jtag-clock clock input to th e jtag circuitry . if the jtag feature is not being utilized, this pin must be connected to v ss . this pin is not available on tqfp packages. cy7c1383c:pin definitions (continued) name tqfp (3-chip enable) bga (1-chip enable) fbga (3-chip enable) i/o description
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 12 of 36 nc 1,2,3,6,7,16,25, 28,29,30,38,39, 51,52,53,56,57, 66,75,78,79,95, 96 b1,b7,c1,c7,d 2,d4,d7,e1,e6, h2,f2,g1,g6,h 7,j3,j5,k1,k6,l 4,l2,l7,m6,n2, n7,l7,p1,p6,r1 ,r5,r7,t1,t4,u 6 a1,a5,b1, b4,b11,c1,c2,c 10,d1,d10,e1,e 10,f1,f10,g1,g 10,h3,h9,h10,j 2,j11,k2,k11, l2,l11,m2,m11, n2,n5,n7,n10, n11,p1,p2,r2 - no connects . not internally connected to the die. 36m, 72m, 144m and 288m are address expansion pins are not internally connected to the die. v ss /dnu 14 - - ground/dnu this pin can be connected to ground or should be left floating. cy7c1383c:pin definitions (continued) name tqfp (3-chip enable) bga (1-chip enable) fbga (3-chip enable) i/o description
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 13 of 36 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t c0 ) is 6.5 ns (133-mhz device). the cy7c1381c/cy7c1383c supports secondary cache in systems utilizing either a linear or interleaved burst sequence. the interleaved burst order supports pentium ? and i486 processors. the linear burst sequence is suited for processors that utilize a linear burst s equence. the burst order is user-selectable, and is determined by sampling the mode input. accesses can be initiated with either the processor address strobe (adsp ) or the controller address strobe (adsc ). address advancement th rough the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burst counter captures the firs t address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualif ied with the byte write enable (bwe ) and byte write select (bw x ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip selects (ce 1 , ce 2 , ce 3 [2] ) and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state control. adsp is ignored if ce 1 is high. single read accesses a single read access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , and ce 3 [2] are all asserted active, and (2) adsp or adsc is asserted low (if the access is initiated by adsc , the write inputs must be deasserted during this first cycle). the address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. if the oe input is asserted low, the requested data will be available at the data outputs a maximum to t cdv after clock rise. adsp is ignored if ce 1 is high. single write accesses initiated by adsp this access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , ce 3 [2] are all asserted active, and (2) adsp is asserted low. the addresses presented are loaded into the address register and the burst inputs ( gw , bwe , and bw x )are ignored during this first clock cycle. if the write inputs are a sserted active ( see write cycle descriptions table for appropriate states that indicate a write) on the next clock rise,the appropriate data will be latched and written into the device.byte writes are allowed. all i/os are tri-stated during a byte write.since this is a common i/o device, the asynchronous oe input signal must be deasserted and the i/os must be tri-stated prior to the presentation of data to dqs. as a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of oe. single write accesses initiated by adsc this write access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , and ce 3 [2] are all asserted active, (2) adsc is asserted low, (3) adsp is deasserted high, and (4) the write input signals (gw , bwe , and bw x ) indicate a write access. adsc is ignored if adsp is active low. the addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. the information presented to dq [a:d] will be written into the specified address location. byte writes are allowed. all i/os are tri-stated when a write is detected, even a byte write. since this is a common i/o device, the asynchronous oe input signal must be deasserted and the i/os must be tri-stated prior to the presentation of data to dqs. as a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of oe . burst sequences the cy7c1381c/cy7c1383c provides an on-chip two-bit wraparound burst counter inside the sram. the burst counter is fed by a [1:0] , and can follow either a linear or interleaved burst order. the burst order is determined by the state of the mode input. a low on mode will select a linear burst sequence. a high on mode will select an interleaved burst order. leaving mode unconnect ed will cause the device to default to a interleaved burst sequence. interleaved burst address table (mode = floating or v dd ) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 14 of 36 sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, da ta integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , ce 3 [2] , adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. . zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz snooze mode standby current zz > v dd ? 0.2v 60 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to snooze curren t this parameter is sampled 2t cyc ns t rzzi zz inactive to exit snooze curre nt this parameter is sampled 0 ns truth table [ 3, 4, 5, 6, 7] cycle description address used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselected cycle, power-down none h x x l x l x x x l-h tri-state deselected cycle, power-down none l l x l l x x x x l-h tri-state deselected cycle, power-down none l x h l l x x x x l-h tri-state deselected cycle, power-down none l l x l h l x x x l-h tri-state deselected cycle, power-down none x x x l h l x x x l-h tri-state snooze mode, pow- er-down none x x x h x x x x x x tri-state read cycle, begin burst external l h l l l x x x l l-h q read cycle, begin burst external l h l l l x x x h l-h tri-state write cycle, begin burst external l h l l h l x l x l-h d read cycle, begin burst external l h l l h l x h l l-h q read cycle, begin burst external l h l l h l x h h l-h tri-state read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h tri-state notes: 3. x=?don't care.? h = logic high, l = logic low. 4. write = l when any one or more byte write enable signals and bwe = l or gw = l. write = h when all byte write enable signals , bwe , gw = h.. 5. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 6. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw x . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the outputs to tri-state. oe is a don't care for the remainder of the write cycle. 7. oe is asynchronous and is not sampled with t he clock rise. it is masked internally during write cycles. during a read cycle all d ata bits are tri-state when oe is inactive or when the device is deselected, and all data bits behave as output when oe is active (low). 9
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 15 of 36 read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h tri-state write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h tri-state read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h tri-state write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d partial truth table for read/write [3, 8] function (cy7c1381c) gw bwe bw d bw c bw b bw a read h h x x x x read hlhhhh write byte a (dq a , dqp a )hlhhhl write byte b(dq b , dqp b )hlhhlh write bytes a, b (dq a , dq b , dqp a , dqp b )h l h h l l write byte c (dq c , dqp c ) hlhlhh write bytes c, a (dq c , dq a, dqp c , dqp a )hlhlhl write bytes c, b (dq c , dq b, dqp c , dqp b )h l h l l h write bytes c, b, a (dq c , dq b , dq a, dqp c , dqp b , dqp a ) hlhlll write byte d (dq d , dqp d )hllhhh write bytes d, a (dq d , dq a, dqp d , dqp a )h l l h h l write bytes d, b (dq d , dq a, dqp d , dqp a )h l l h l h write bytes d, b, a (dq d , dq b , dq a, dqp d , dqp b , dqp a ) hllhll write bytes d, b (dq d , dq b, dqp d , dqp b )h l l l h h write bytes d, b, a (dq d , dq c , dq a, dqp d , dqp c , dqp a ) hlllhl write bytes d, c, a ( dq d , dq b , dq a, dqp d , dqp b , dqp a ) hllllh write all bytes hlllll write all bytes l x x x x x note: 8. table only lists a partial listing of the byte write combinations. any combination of bw x is valid appropriate write will be done bas ed on which byte write is active. truth table for read/write [3] function (cy7c1383c) gw bwe bw b bw a read h h x x read h l h h write byte a - ( dq a and dqp a )hlhl write byte b - ( dq b and dqp b )hllh write all bytes h l l l truth table [ 3, 4, 5, 6, 7] cycle description address used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 16 of 36 write all bytes l x x x truth table for read/write [3] function (cy7c1383c) gw bwe bw b bw a
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 17 of 36 ieee 1149.1 serial boundary scan (jtag) the cy7c1381c/cy7c1383c incorporates a serial boundary scan test access port (tap). this port operates in accordance with ieee standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. these functions from the ieee specificatio n are excluded because their inclusion places an added delay in the critical speed path of the sram. note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec-standard 3.3v or 2.5v i/o logic levels. the cy7c1381c/cy7c1383c contains a tap controller, instruction register, boundary sc an register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low(v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alter- nately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. tap controller state diagram the 0/1 next to each state repr esents the value of tms at the rising edge of tck. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see figure . tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most signif- icant bit (msb) of any regist er. (see tap controller block diagram.) test data-out (tdo) the tdo output ball is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (see tap controller state diagram.) tap controller block diagram performing a tap reset a reset is performed by forc ing tms high (vdd) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . s election circuitr y selection circuitry tck t ms tap controller tdi td o
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 18 of 36 instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the x36 configuration has a 70-bit-long register and the x18 configuration has a 51-bit long register. the boundary scan register is lo aded with the contents of the ram i/o ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction regi ster. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set overview eight different instructions are possible with the three bit instruction register. all combinations are listed in the instruction codes table. three of these instructions are listed as reserved and should not be used. the other five instruc- tions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller cannot be used to load address data or control signals into the sram and cannot preload the i/o buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather, it per forms a capture of the i/o ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this stat e, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instructi on register is loaded with all 0s. extest is not implemented in this sram tap controller, and therefore this device is not compliant to 1149.1. the tap controller does recognize an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. there is one difference between the two instructions. un like the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo balls when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 m andatory instruction. the preload portion of this instru ction is not implemented, so the device tap controller is not fully 1149.1 compliant. when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. the user must be aware that th e tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the ta p may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guar antee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller?s capture setup plus hold time (t cs plus t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if th is is an issue, it is still
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 19 of 36 possible to capture all other signals and simply ignore the value of the clk captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo balls. note that since the preload part of the command is not implemented, putting the tap to the update-dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in t he instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instructio n is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions. tap timing tap ac switching characteristics over the operating range [9, 10] parameter symbol min max units clock tck clock cycle time t tcyc 100 ns tck clock frequency t tf 10 mhz tck clock high time t th 40 ns tck clock low time t tl 40 ns output times tck clock low to tdo valid t tdov 20 ns tck clock low to tdo invalid t tdox 0ns setup times tms set-up to tck clock rise t tmss 10 ns tdi set-up to tck clock rise t tdis 10 ns capture set-up to tck rise t cs 10 hold times tms hold after tck clock rise t tmsh 10 ns tdi hold after clock rise t tdih 10 ns capture hold after clock rise t ch 10 ns notes: 9. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 10. test conditions are specified using t he load in tap ac test conditions. t r /t f = 1ns t tl test clock (tck) 123456 t est mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov don?t care undefined
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 20 of 36 3.3v tap ac test conditions input pulse levels ........ ........................................v ss to 3.3v input rise and fall times ........... ........... ..............................1ns input timing reference levels ...........................................1.5v output reference levels...................................................1.5v test load termination supply voltage...............................1.5v 3.3v tap ac output load equivalent 2.5v tap ac test conditions input pulse levels............................................... v ss to 2.5v input rise and fall time ......................................................1ns input timing reference levels...... ............. ......................1.25v output reference levels ............. ..... ..............................1.25v test load termination supply voltage .................... ........1.25v 2.5v tap ac output load equivalent note: 11. all voltages referenced to v ss (gnd). t do 1.5v 20p f z = 50 ? o 50 ? t do 1.25v 20p f z = 50 ? o 50 ? tap dc electrical characteristics and operating conditions (0c < ta < +70c; vdd = 3.3v 0.165v unless otherwise noted) [11] parameter description descript ion conditions min max units v oh1 output high voltage i oh = -4.0 ma v ddq = 3.3v 2.4 v i oh = -1.0 ma v ddq = 2.5v 2.0 v v oh2 output high voltage i oh = -100 a v ddq = 3.3v 2.9 v v ddq = 2.5v 2.1 v v ol1 output low voltage i ol = 8.0 ma v ddq = 3.3v 0.4 v i ol = 8.0 ma v ddq = 2.5v 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 3.3v 0.2 v v ddq = 2.5v 0.2 v v ih input high voltage v ddq = 3.3v 2.0 v dd + 0.3 v v ddq = 2.5v 1.7 v dd + 0.3 v v il input low voltage v ddq = 3.3v -0.3 0.8 v v ddq = 2.5v -0.3 0.7 v i x input load current gnd < v in < v ddq -5 5 a
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 21 of 36 identification register definitions instruction field cy7c1381c (512kx36) cy7c1383c (1mx18) description revision number (31:29) 010 010 describes the version number. device depth (28:24) 01010 01010 reserved for internal use device width (23:18) 000001 000001 defines memory type and architecture cypress device id (17:12) 100101 010101 defines width and density cypress jedec id code (11:1) 00000110100 00000110100 allows unique identification of sram vendor. id register presence indicator (0) 11 indicates the presence of an id register. scan register sizes register name bit size(x36) bit size(x18) instruction 33 bypass 11 id 32 32 boundary scan order 72 72 identification codes instruction code description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1 compliant. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruction is reserved for future use. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. does not affect sram operation. this in struction does not implement 1149.1 preload function and is therefor e not 1149.1 compliant. reserved 101 do not use: this instruction is reserved for future use. reserved 110 do not use: this instruction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations.
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 22 of 36 119-ball bga boundary scan order cy7c1381c (512k x 36) bit # ball id bit # ball id 1 k4 37 b2 2 h4 38 p4 3m439 n4 4f440 r6 5b441 t5 6a442 t3 7g443 r2 8c644 r3 9a645 p2 10 d6 46 p1 11 d7 47 n2 12 e6 48 l2 13 g6 49 k1 14 h7 50 n1 15 e7 51 m2 16 f6 52 l1 17 g7 53 k2 18 h6 54 not bonded (preset to 0) 19 t7 55 h1 20 k7 56 g2 21 l6 57 e2 22 n6 58 d1 23 p7 59 h2 24 k6 60 g1 25 l7 61 f2 26 m6 62 e1 27 n7 63 d2 28 p6 64 a5 29 b5 65 a3 30 b3 66 e4 31 c5 67 internal 32 c3 68 l3 33 c2 69 g3 34 a2 70 g5 35 t4 71 l5 36 b6 72 internal
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 23 of 36 cy7c1383c (1m x 18) bit # ball id bit # ball id 1 k4 37 b2 2 h4 38 p4 3m439 n4 4f440 r6 5b441 t5 6a442 t3 7g443 r2 8c644 r3 9 a6 45 not bonded (preset to 0) 10 t6 46 not bonded (preset to 0) 11 not bonded (preset to 0) 47 not bonded (preset to 0) 12 not bonded (preset to 0) 48 not bonded (preset to 0) 13 not bonded (preset to 0) 49 p2 14 d6 50 n1 15 e7 51 m2 16 f6 52 l1 17 g7 53 k2 18 h6 54 internal 19 t7 55 h1 20 k7 56 g2 21 l6 57 e2 22 n6 58 d1 23 p7 59 not bonded (preset to 0) 24 not bonded (preset to 0) 60 not bonded (preset to 0) 25 not bonded (preset to 0) 61 not bonded (preset to 0) 26 not bonded (preset to 0) 62 not bonded (preset to 0) 27 not bonded (preset to 0) 63 not bonded (preset to 0) 28 not bonded (preset to 0) 64 a5 29 b5 65 a3 30 b3 66 e4 31 c5 67 internal 32 c3 68 not bonded (preset to 0) 33 c2 69 internal 34 a2 70 g3 35 t2 71 l5 36 b6 72 internal 119-ball bga boundary scan order
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 24 of 36 165-ball fbga boundary scan order cy7c1381c (512k x 36) bit# ball id bit# ball id 1b637n6 2b738r6 3a739p6 4b840r4 5a841r3 6b942p4 7a943p3 8b1044r1 9a1045n1 10 c11 46 l2 11 e10 47 k2 12 f10 48 j2 13 g10 49 m2 14 d10 50 m1 15 d11 51 l1 16 e11 52 k1 17 f11 53 j1 18 g11 54 not bonded (preset to 0) 19 h11 55 g2 20 j10 56 f2 21 k10 57 e2 22 l10 58 d2 23 m10 59 g1 24 j11 60 f1 25 k11 61 e1 26 l11 62 d1 27 m11 63 c1 28 n11 64 a2 29 r11 65 b2 30 r10 66 a3 31 r9 67 b3 32 r8 68 b4 33 p10 69 a4 34 p9 70 a5 35 p8 71 b5 36 p11 72 a6
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 25 of 36 cy7c1383c (1m x 18) bit# ball id bit# ball id 1b637n6 2b738r6 3a739p6 4b840r4 5a841r3 6b942p4 7a943p3 8b1044r1 9 a10 45 not bonded (preset to 0) 10 a11 46 not bonded (preset to 0) 11 not bonded (preset to 0) 47 not bonded (preset to 0) 12 not bonded (preset to 0) 48 not bonded (preset to 0) 13 not bonded (preset to 0) 49 n1 14 c11 50 m1 15 d11 51 l1 16 e11 52 k1 17 f11 53 j1 18 g11 54 not bonded (preset to 0) 19 h11 55 g2 20 j10 56 f2 21 k10 57 e2 22 l10 58 d2 23 m10 59 not bonded (preset to 0) 24 not bonded (preset to 0) 60 not bonded (preset to 0) 25 not bonded (preset to 0) 61 not bonded (preset to 0) 26 not bonded (preset to 0) 62 not bonded (preset to 0) 27 not bonded (preset to 0) 63 not bonded (preset to 0) 28 not bonded (preset to 0) 64 a2 29 r11 65 b2 30 r10 66 a3 31 r9 67 b3 32 r8 68 not bonded (preset to 0) 33 p10 69 not bonded (preset to 0) 34 p9 70 a4 35 p8 71 b5 36 p11 72 a6 165-ball fbga boundary scan order
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 26 of 36 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v dd relative to gnd........ ?0.3v to +4.6v dc voltage applied to outputs in tri-state........................................... ?0.5v to v ddq + 0.5v dc input voltage....................................?0.5v to v dd + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ ........... >2001v (per mil-std-883, method 3015) latch-up current..................................................... >200 ma operating range range ambient temperature v dd v ddq commercial 0c to +70c 3.3v ? 5%/+10% 2.5v ? 5% to v dd industrial -40c to +85c electrical characteristics over the operating range [12, 13] parameter description test conditions min. max. unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage v ddq = 3.3v 3.135 v dd v v ddq = 2.5v 2.375 2.625 v v oh output high voltage v ddq = 3.3v, v dd = min., i oh = ?4.0 ma 2.4 v v ddq = 2.5v, v dd = min., i oh = ?1.0 ma 2.0 v v ol output low voltage v ddq = 3.3v, v dd = min., i ol = 8.0 ma 0.4 v v ddq = 2.5v, v dd = min., i ol = 1.0 ma 0.4 v v ih input high voltage [12] v ddq = 3.3v 2.0 v dd + 0.3v v v ddq = 2.5v 1.7 v dd + 0.3v v v il input low voltage [12] v ddq = 3.3v ?0.3 0.8 v v ddq = 2.5v ?0.3 0.7 v i x input load gnd v i v ddq ?5 5 a input current of mode input = v ss ?30 a input = v dd 30 a input current of zz input = v ss ?30 a input = v dd 30 a i oz output leakage current gnd v i v dd, output disabled ?5 5 a i os output short circuit current v dd = max., v out = gnd -300 a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 7.5-ns cycle, 133 mhz 210 ma 8.8-ns cycle, 117 mhz 190 ma 10-ns cycle, 100 mhz 175 ma i sb1 automatic ce power-down current?ttl inputs max. v dd , device deselected, v in v ih or v in v il , f = f max, inputs switching 7.5-ns cycle, 133 mhz 120 ma 8.8-ns cycle, 117 mhz 110 ma 10-ns cycle, 100 mhz 100 i sb2 automatic ce power-down current?cmos inputs max. v dd , device deselected, v in v dd ? 0.3v or v in 0.3v, f = 0, inputs static all speeds 70 ma i sb3 automatic ce power-down current?cmos inputs max. v dd , device deselected, v in v ddq ? 0.3v or v in 0.3v, f = f max , inputs switching 7.5-ns cycle, 133 mhz 105 ma 8.8-ns cycle, 117 mhz 100 ma 10-ns cycle, 100 mhz 95 ma i sb4 automatic ce power-down current?ttl inputs max. v dd , device deselected, v in v dd ? 0.3v or v in 0.3v, f = 0, inputs static all speeds 80 ma notes: 12. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2), undershoot: v il (ac) > -2v (pulse width less than t cyc /2). 13. t power-up : assumes a linear ramp from 0v to v dd (min.) within 200ms. during this time v ih < v dd and v ddq < v dd
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 27 of 36 thermal resistance [14] parameter description test conditions tqfp package bga package fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedence, per eia / jesd51. 31 45 46 c/w jc thermal resistance (junction to case) 6 7 3 c/w capacitance [14] parameter description test conditions tqfp package bga package fbga package unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3v. v ddq = 2.5v 5 8 9 pf c clk clock input capacitance 5 8 9 pf c i/o input/output capacitance 5 8 9 pf notes: 14. tested initially and after any design or process change that may affect these parameters ac test loads and waveforms output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.5v 3.3v all input pulses v dd gnd 90% 10% 90% 10% 1ns 1ns (c) output r = 1667 ? r =1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.25v 2.5v all input pulses v dd gnd 90% 10% 90% 10% 1ns 1ns (c) 3.3v i/o test load 2.5v i/o test load
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 28 of 36 switching characteristics over the operating range [19, 20] parameter description 133 mhz 117 mhz 100 mhz unit min. max. min. max. min. max. t power v dd (typical) to the first access [15] 1 11 ms clock t cyc clock cycle time 7.5 8.5 10 ns t ch clock high 2.1 2.3 2.5 ns t cl clock low 2.1 2.3 2.5 ns output times t cdv data output valid after clk rise 6.5 7.5 8.5 ns t doh data output hold after clk rise 2.0 2.0 2.0 ns t clz clock to low-z [16, 17, 18] 2.0 2.0 2.0 ns t chz clock to high-z [16, 17, 18] 0 4.0 0 4.0 0 5.0 ns t oev oe low to output valid 3.2 3.4 3.8 ns t oelz oe low to output low-z [16, 17, 18] 0 0 0 ns t oehz oe high to output high-z [16, 17, 18] 4.0 4.0 5.0 ns setup times t as address set-up before clk rise 1.5 1.5 1.5 ns t ads adsp , adsc set-up before clk rise 1.5 1.5 1.5 ns t advs adv set-up before clk rise 1.5 1.5 1.5 ns t wes gw , bwe , bw [a:d] set-up before clk rise 1.5 1.5 1.5 ns t ds data input set-up before clk rise 1.5 1.5 1.5 ns t ces chip enable set-up 1.5 1.5 1.5 ns hold times t ah address hold after clk rise 0.5 0.5 0.5 ns t adh adsp , adsc hold after clk rise 0.5 0.5 0.5 ns t weh gw , bwe , bw [a:d] hold after clk rise 0.5 0.5 0.5 ns t advh adv hold after clk rise 0.5 0.5 0.5 ns t dh data input hold after clk rise 0.5 0.5 0.5 ns t ceh chip enable hold after clk rise 0.5 0.5 0.5 ns notes: 15. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd ( minimum) initially, before a read or write operation can be initiated. 16. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in part (b) of ac test loads. transition is measured 200 mv from steady-state vo ltage. 17. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but re flect parameters guaranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions 18. this parameter is sampled and not 100% tested. 19. timing reference level is 1.5v when v ddq = 3.3v and is 1.25v when v ddq = 2.5v. 20. test conditions shown in (a) of ac test loads unless otherwise noted.
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 29 of 36 timing diagrams read cycle timing [21] t cyc t cl clk t adh t ads address t ch t ah t as a1 t ceh t ces data out (q) high-z t clz t doh t cdv t oehz t cdv single read burst read t oev t oelz t chz burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a2 + 2) q(a2 + 3) a2 adv suspends burst deselect cycle don?t care undefined adsp adsc g w, bwe,bw x ce adv oe
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 30 of 36 10 write cycle timing [21, 22] timing diagrams (continued) t cyc t cl clk t adh t ads address t ch t ah t as a1 t ceh t ces high-z burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds t weh t wes byte write signals are ignored for first cycle when adsp initiates burst adsc extends burst adv suspends burst don?t care undefined adsp adsc bwe, bw x gw ce adv oe data in (d) d ata out (q)
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 31 of 36 read/write cycle timing [21, 23, 24] note: 21. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. 22. full width write can be initiated by either gw low; or by gw high, bwe low and bw x low. 23. the data bus (q) remains in high-z following a write cycle, unless a new read ac cess is initiated by adsp or adsc . 24. gw is high. 25. device must be deselected when entering zz mode. see cycle descr iptions table for all possible signal conditions to deselect the device. 26. dqs are in high-z when exiting zz sleep mode. timing diagrams (continued) t cyc t cl clk t adh t ads address t ch t ah t as a2 t ceh t ces single write d(a3) a3 a4 burst read back-to-back reads high-z q(a2) q(a4) q(a4+1) q(a4+2) q(a4+3) t weh t wes t oehz t dh t ds t cdv t oelz a1 a5 a6 d(a5) d(a6) q(a1) back-to-back writes don?t care undefined adsp adsc bwe, bw x ce adv oe data in (d) d ata out (q)
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 32 of 36 ordering information speed (mhz) ordering code package name part and package type operating range 133 cy7c1381c-133ac cy7c1383c-133ac a101 100-lead thin quad flat pack (14 x 20 x 1.4mm) 3 chip enables commercial cy7c1381c-133bgc cy7c1383c-133bgc bg119 119-ball (14 x 22 x 2.4 mm) bga 3 chip enables and jtag cy7c1381c-133bzc cy7c1383c-133bzc bb165a 165-ball fine-pitch ball grid array (13 x 15 x 1.2mm) 3 chip enables and jtag 117 cy7c1381c-117ac a101 100-lead thin quad flat pack (14 x 20 x 1.4mm) 3 chip enables commercial cy7c1383c-117ac cy7c1381c-117bgc bg119 119-ball (14 x 22 x 2.4 mm) bga 3 chip enables and jtag CY7C1383C-117BGC cy7c1381c-117bzc cy7c1383c-117bzc bb165a 165-ball fine-pitch ball grid array (13 x 15 x 1.2mm) 3 chip enables and jtag cy7c1381c-117ai cy7c1383c-117ai a101 100-lead thin quad flat pack (14 x 20 x 1.4mm) 3 chip enables industrial cy7c1381c-117bgi cy7c1383c-117bgi bg119 119-ball (14 x 22 x 2.4 mm) bga 3 chip enables and jtag cy7c1381c-117bzi cy7c1383c-117bzi bb165a 165-ball fine-pitch ball grid array (13 x 15 x 1.2mm) 3 chip enables and jtag timing diagrams (continued) z z mode timing [25 , 26] t zz i supply clk zz t zzrec a ll inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only
cy7c1381c cy7c1383c document #: 38-05238 rev. *b page 33 of 36 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. 100 cy7c1381c-100ac cy7c1383c-100ac a101 100-lead thin quad flat pack (14 x 20 x 1.4mm) 3 chip enables commercial cy7c1381c-100bgc bg119 119-ball (14 x 22 x 2.4 mm) bga 3 chip enables and jtag cy7c1383c-100bgc cy7c1381c-100bzc bb165a 165-ball fine-pitch ball grid array (13 x 15 x 1.2mm) 3 chip enables and jtag cy7c1383c-100bzc cy7c1381c-100ai a101 100-lead thin quad flat pack (14 x 20 x 1.4mm) 3 chip enables industrial cy7c1383c-100ai cy7c1381c-100bgi bg119 119-ball (14 x 22 x 2.4 mm) bga 3 chip enables and jtag cy7c1383c-100bgi cy7c1381c-100bzi bb165a 165-ball fine-pitch ball grid array (13 x 15 x 1.2mm) 3 chip enables and jtag cy7c1383c-100bzi shaded areas contain advance information. please contact your local sales represent ative for availability of these parts. package diagrams ordering information speed (mhz) ordering code package name part and package type operating range dimensions are in millimeters. 0.300.08 0.65 20.000.10 22.000.20 1.400.05 121 1.60 max. 0.05 min. 0.600.15 0 min. 0.25 0-7 (8x) stand-off r 0.08 min. typ. 0.20 max. 0.15 max. 0.20 max. r0.08min. 0.20 max. 14.000.10 16.000.20 0.10 see detail a detail a 1 100 30 31 50 51 80 81 gauge plane 1.00 ref. 0.20 min. seating plane 100-pin thin plastic quad flat pack (14 x 20 x 1.4 mm) a101 51-85050-*a
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 34 of 36 package diagrams (continued) 51-85115-*b
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 35 of 36 package diagrams (continued) i486 is a trademark, and intel and pentium are registered trade marks of intel corporation. po werpc is a trademark of ibm corporation. all product and company names mentioned in this document are the trademarks of their respective holders. 165-ball fbga (13 x 15 x 1.2 mm) bb165a 51-85122-*c
cy7c1381 c cy7c1383 c document #: 38-05238 rev. *b page 36 of 36 document history page document title: cy7c1381c/cy7c1383c 18-mb (512k x 36/1m x 18) flow-through sram document number: 38-05238 rev. ecn no. issue date orig. of change description of change ** 116278 08/27/02 skx new data sheet *a 121541 11/21/02 dsg updated package diagrams 51-85115 (bg119) to rev. *b and 51-85122 (bb165a) to rev. *c *b 206081 see ecn rkf final datasheet

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